The invention generally relates to a semiconductor device. More particularly, the invention relates to a semiconductor comprising of a fin-transistor and a method for fabricating the same.
In a fin-channel-array-transistor (FCAT), a fin channel transistor has a three-dimensional structure where a tri-gate surrounds a channel. It is possible to manufacture the fin channel structure with existing manufacturing technology. The fin channel structure has more surface area to reduce short channel effects between a drain region and a source region. The fin channel structure allows a reduction in channel doping concentration which reduces leakage current through a junction region.
A lower gate electrode of the fin channel transistor includes a p+ polysilicon layer. A work function of the p+ polysilicon layer is larger than that of a p− silicon substrate. Using a DRAM cell as an example, when there is a binary “1” voltage in the drain region while the fin channel transistor is turned off, a leakage current in the drain region is increased due to a gate induced drain leakage (“GIDL”) phenomenon. As a result, data retention of a DRAM cell (in this case “1”) is reduced which degrades a refresh characteristic of the DRAM.